Intel has interduced another sleep state towards Intel chipset 6 series known as deep sleep state .
Now our board with Intel chipset 6 has four wells ,
1. RTC well .
2. Deep sleep well.
3. Suspend well. And
4. Core well.
Deep sleep well is interduced to save more power. Because EC release S5_ON , when deep sleep well meet its conditions and comunicate to EC for further proceedings .
How does it works?
Pch got an other section which is known as DSW . As it recives the power from the same source RTC VCC and DSW power good (or designed by vander.)
1. PCH releases SUSWARN# signal for the EC .
2. EC acknowledges back through SUS_ACK# . that I am ready to release the s5_on signal .
3. Then pch sends the signal SLP_SUS# to ec controler .
These all # signals must be high while turning on the board.
And EC release the S5_ON signal for the further proceedings .
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